|Name||Engr. Noshina Ishaaq|
|Department||Computer Engineering (Taxila)|
|Highest Qualification||MS Engg. UET Taxila|
Bsc Computer Engineering(UET Taxila)
Project Proposals for 2K7
FPGA Design and implementation of the RS Decoder:
This project presents FPGA and VLSI implementations of an 8-bit error correcting (207,187) Reed-Solomon (RS) decoder architecture .The decoder will use the Euclidian algorithm for the solving of the key equation for the error-locator polynomial, σ(x), and error-value polynomial, ω(x). The RS decoder will be implemented on a Xilinx Virtex FPGA chip .
Resuable IP Core for FEC code:
Forward Error Correcting code like Viterbi is a new class of code that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratio. These codes achieve a near-Shannon limit performance. The Viterbi-Algorithm is a basic part of the coding and modulation method of the digital data transmission.
High Speed Lossless Data Compression:
This project represents a sequential algorithm(Lz1) that compresses strings of binary bytes of variable length into a fixed length compressed format.The two important steps in the algorithm are string parsing and coding. The major work in data compression is the reduction of repeated strings of incoming data into compact code words.
A CPU Scheduling Algorithm Simulator:
This project presents a simulator that uses graphical animation to convey the concepts of various scheduling algorithms for a single CPU. The simulator supports various types of CPU scheduling algorithms. For each algorithm, the user can use the predefined scheduling parameters and the predefined set of processes or the user can customize them.