Name | Dr. Syed Azhar Ali Zaidi |
Designation | Assistant Professor |
Department | Electronics Engineering (Taxila) |
Highest Qualification | |
Specialization | ASIC Design, Digital Architectures for Communications |
Phone No | 051-9047722 |
Cell No | |
Fax No | 051-9047420 |
[email protected] |
University of Engineering and Technology Taxila, Pakistan, 2008
University of Engineering and Technology Taxila, Pakistan, 2011
Politecnico di Torino, Italy, 2015
Journals
[1] S.A.A.Zaidi, A. Tuoheti, M.Martina and G.Masera,"FPGA accelerator of Algebraic Quasi Cyclic LDPC Codes for NAND flash memories," in Design & Test, IEEE
[2] M. Awais, A. Ahmed, S. A. Ali, M. Naeem, W. Ejaz and A. Anpalagan, "Resource Management in Multicloud IoT Radio Access Network," in IEEE Internet of Things Journal, vol. 6, no. 2, pp. 3014-3023, April 2019, doi: 10.1109/JIOT.2018.2878511.
[3] Ijaz M, Zaidi SAA, Rashid A (2021) Uniform patterns based area-efficient and accurate stochastic computing finite impulse response filter. PLOS ONE 16(1): e0245943. https://doi.org/10.1371/journal.pone.0245943
[4] Raza H, Zaidi SAA, Rashid A, Haider S (2021) An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder. PLOS ONE 16(3): e0249269. https://doi.org/10.1371/journal.pone.0249269
Conference Papers
[1] S.A.A.Zaidi, M.Awais, C.Condo, M.Martina and G.Masera,"FPGA accelerator of Quasi Cyclic EG-LDPC Codes decoder for NAND flash memories": In Design and Architectures for Signal and Image Processing(DASIP), 2013 Conference on, pages 190-195, 2013.
[2] S.A.A. Zaidi, M. Martina, and G. Masera., “Rapid Prototyping of Floating Point AWGN Channel Using High Level Synthesis”. In Forum on Specification and Design Languages (FDL), 2014 Conference on, paper 46, Oct 2014.
[3] A. Zahir, S.A.A. Zaidi, A. Pulimeno, M. Graziano, D. Demarchi, G. Masera and G. Piccinini., “Molecular transistor circuits: From device model to circuit simulation”. In Nanoscale Architectures (NANOARCH), 2014 IEEE/ACM International Symposium on, Paris, pp. 129-134, July 2014.
[4] G.Xiao, W.Ahmad, S.A.A. Zaidi, M. Ruo Roch, G. Causapruno.,“High Speed VLSI Architecture for Finding the First W Maximum/minimum Values”. In Applications in Electronics Pervading Industry, Environment & Society (APPLEPIES), 2014 Conference on, paper 5, May 2014.
Undergraduate Courses
Postgraduate Courses
Taught Laboratories