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Name Dr. Yaseer Arafat Durrani
Designation Associate Professor
Department Department of Electronic Engineering
Phone No 051-9047-720
Cell No
Fax No 051-9047-420
Email [email protected]

• Ph.D. in Electronic Engineering, Polytechnic University of Madrid, Spain (2008)

• M.Phil. in Electronic Engineering, Polytechnic University of Madrid, Spain (2005)

• M.Sc. in Electronic Engineering, Royal Institute of Technology, Sweden (2002)

• B.Sc. in Electrical & Electronic Engineering, Eastern Mediterranean University, N. Cyprus, Turkey(1999)

• B.Sc. in Physics & Mathematics, University of Peshawar, Pakistan (1995)

For the past twelve years with academic/industrial experience, I had various opportunities to serve in different Universities/Industrial Organizations and had been actively involved in Research and Design Projects around the Globe. My accumulated work essentially spanned the entire domain of Electronic System Design from top to bottom level. I have specialized in the field of Low-power 2D/3D System-on-Chip (SoC) design and particularly in Embedded Systems. In general, my research interest includes Low Power Embedded Systems, SoC design, Nano Devices and Computer Architecture.

As regards my academic/industrial experience, I had various opportunities to serve in different Universities/Industrial Organizations and had been actively involved in Research & Design Projects around the Globe. Currently I am working as Associate Professor at the Department of Electronics Engineering, UET, Taxila. Previously, I had served in Qassim University, Saudi Arabia, University of the Punjab and GIK Institute of Engineering Sciences & Technology, Pakistan. I was invited as a Visiting Researcher at Ryerson University and University of Victoria, Canada in the field of Computer Architecture design. I had also worked as Test Engineer in Celestica, Canada and Design Engineer in Infineon Technologies AG, Germany.

I have specialized in the field of 2D/3D System-on-Chip (SoC) design and particularly in Low Power Embedded Systems. My research has been focused in power modeling of SoC and its subsystem of Network-on-Chip (NoC) design in 2D/3D ICs. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation. The power macromodeling technique uses the input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses/TSVs in MPSoC design at high-level. In general, my research interest includes Low Power Embedded Systems, MPSoC design, Nano Devices and Computer Architecture.

I am honoured of being a member of IEEE, and PEC. I have published more than 40 technical papers in different International Journals and Conferences. Currently, my book “Digital Logic Analysis & Design” is under revision and is going to be published soon.

  • 3D System-on-Chip Design
  • Low Power Embedded System
  • VLSI/Nano Devices
  • Sensors & Bioelectronics
  1. Yaseer A. Durrani “Power and Thermal Modeling Approach for Homogeneously Stacked Butterfly Fat Tree Architecture in 3D ICs” Wiley International Journal of Numerical Modeling, Electronic Networks, Devices & Fields, Vol. 31, no. 1, DOI:10.1002/jnm.2330, 2018, ISSN: 1099-1204, (IF: 0.515)
  2. Yaseer A. Durrani “Power Macro-Modeling Technique for NoC-based Homogeneous Layered 3D ICs” Wiley International Journal of Numerical Modeling, Electronic Networks, Devices & Fields, Vol. 30, no. 6, DOI:10.1002/jnm.2309, 2017, ISSN: 1099-1204, (IF: 0.515)
  3. Yaseer A. Durrani “Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs” World Scientific Journal of Circuits, Systems and Computers, Vol. 27, no. 2, pp. 1-16, 2018, Print ISSN: 0218-1266, Online ISSN: 1793-6454, https://doi.org/10.1142/S0218126618500342 (IF: 0.47)
  4. Yaseer A. Durrani, T. Riesgo “Power modeling for High Performance network-on-chip architectures” Elsevier Journal of Microprocessors & Microsystems, Vol. 50, pp. 80-89, 2017, ISSN:0141-9331, DOI:10.1016/j.micpro.2017.03.003, (IF: 0.571)
  5. K. Mahmood, A. Rafique, Yaseer A. Durrani “Effect of Isothermal Treatment on Ni3Al Coatings Deposited by Air Plasma Spraying System, Journal Archives of Metallurgy and Materials, Vol. 63, no. 1, ISSN: 1733-3490, 2018 (IF: 0.571)
  6. Yaseer A. Durrani, T. Riesgo “Efficient Power Analysis Approach and its Application to System-on-Chip Design” Elsevier Journal of Microprocessors & Microsystems, Vol. 46, no. 45, part A, pp. 11-20, 2016, ISSN:0141-9331, DOI:10.1016/j.micpro.2016.09.003, (IF: 0.571) (Oct, 2016)
  7. Yaseer A. Durrani, T. Riesgo “Power Macro-Modelling Technique and its application to SoC-based Design” Wiley International Journal of Numerical Modeling, Electronic Networks, Devices & Fields, Vol 29, no.6, 2016, ISSN: 1099-1204, DOI: 10.1002/jnm.2207, (IF: 0.515)
  8. Yaseer A. Durrani, T. Riesgo, M. I. Khan, T. Mahmood “Power Analysis approach and its application to IP-based SoC design” Emerald Group Publisher, International Journal of Computation and Mathematics in Electrical and Electronic Engineering” Vol. 35, Issue 3, pp. 1218-1236, 2016, ISSN: 0332-1649. (IF: 0.371)
  9. A. N. Khan, S. H. Khan, Y. A. Durrani "Microstructural Evaluation of High-Strength Bainitic Steel" Journal of Materials Evaluation” The American Society for Nondestructive Testing, Vol. 74, No. 11, pp. 1567-1573, 2016, ISSN, 0025-5327. (IF: 0.255)
  10. M. M. Rauf, M. Shahid, Y. A. Durrani, A. N. Khan, A. Hussain, R. Akhter “Cladding of Ni-20Cr Coating by Optimizing the CO2 Laser Parameters” Springer Arabian Journal of Science & Engineering, ISSN: 1319-8025, Vol. 41, No. 6, pp. 2353-2362, 2015, DOI 10.1007/s13369-015-1972-7. (IF: 0.367) (8-Dec. 2015)
  11. I. N. Qureshi, M. Shahid, A. N. Khan, Y. A. Durrani “Evaluation of Titanium Nitride –Modified Bondcoat System Used in Thermal Barrier Coating in Corrosive Salts Environment at High Temperature” Springer Journal of Thermal Spray Technology, Vol. 24, No. 8, pp. 1520-1528, DOI:10.1007/s11666-015-0344-x, 2015, ISSN: 1059-9630. (IF: 1.344)
  12. Yaseer A. Durrani, T. Riesgo “High-Level Power Analysis for Intellectual Property-Based Digital Systems” Springer Journal of Circuits, Systems & Signal Processing, Vol. 33, No. 6, pp. 1035-1051,:10.1007/s00034-013-9692-2, 2013, Print ISSN 028-081X, Online ISSN 1531-5878, (IF: 0.982) (28.Nov. 2013)
  13. Yaseer A. Durrani, T. Riesgo “Power Estimation Technique for DSP Architecture”, Elsevier Journal of Digital Signal Processing, Vol. 19, Issue 2, pp.213-219, 2009, ISSN:1051-2004, (IF:1.871)
  14. Yaseer A. Durrani “Power Optimization using Low-Transition Rate based LFSR Pattern Generator”, Technical Journal, UET, Taxila, Vol. 22, No. 2, pp. 60-65, ISSN: 1813-1786, June, 2017.
  15. Yaseer A. Durrani “Fundamentals of Low-Noise in Analog Circuits”, Technical Journal, UET, Taxila, Vol. 22, No. 1, pp. 46-51, ISSN: 1813-1786, Jan, 2017.
  16. Yaseer A. Durrani “Design of High Performance IIR filter Using Vedic Multiplier Method”, Technical Journal, UET, Taxila, Vol. 21, No. 4, pp. 46-51, ISSN: 1813-1786, Oct, 2016.
  17. Yaseer A. Durrani “Design of Fourth Order Active Band-pass Filter with Sallen & Key Topology”, Technical Journal, UET, Taxila, Vol. 21, No. 3, pp. 51-56, ISSN: 1813-1786, July, 2016.
  18. Yaseer A. Durrani, A. Ahmad “Hybrid Power Analysis Approach for Electronic System Design”, Technical Journal, UET, Taxila, Vol. 21, No.2, pp. 26-32, April, 2016, ISSN: 1813-1786.
  19. Yaseer A. Durrani “Low-Power Integrated Circuit Design Approach” Technical Journal, UET, Taxila, Vol. 21, No.1, pp. 32-42, Jan, 2016, ISSN: 1813-1786.
  20. Yaseer A. Durrani “Linear Regression-Based Power Analysis for Digital Electronic Systems” Technical Journal, UET, Taxila, Vol. 20, No. 4, pp. 44-48, Oct. 2015, ISSN: 1813-1786.
  21. Yaseer A. Durrani “High Level Power Optimization for Array Multipliers”, Journal of the Nucleus, Vol. 50, No. 4, pp. 351-358, 2013, ISSN: 0029-5698
  22. Yaseer A. Durrani “Accurate Power Analysis for Conventional MOS Transistors Using 0.12um Technology” Journal of the Nucleus, Vol. 50, No. 4, pp. 341-350, 2013, ISSN: 0029-5698.
  23. Yaseer A. Durrani, T. Riesgo "High-Level Power Analysis for IP-Based Digital Systems" American Scientific Publisher, Journal of Low Power Electronics, Vol. 9, No. 4, pp. 435-444, 2013, ISSN: 1546-1998, (IF: 0.485)
  24. Yaseer A. Durrani, T. Riesgo “Architectural Power Analysis for Intellectual Property-Based Digital System”, American Scientific Publisher, Journal of Low Power Electronics, Vol. 3, No. 3, pp. 271-279(9), 2007, ISSN:1546-1998, (IF:0.485)
  25. Yaseer A. Durrani, Teresa Riesgo “Power Estimation for Intellectual Property-Based Digital Systems at Architectural Level” Elsevier Journal of King Saud University-Computer and Information Sciences, Vol. 26, No. 3, pp. 287-295, DOI:10.1016/j.jksuci.2014.03.005, 2014, ISSN: 1319-1578.
  26. Yaseer A. Durrani “Power Analysis for Deep Submicrometer Conventional MOS Transistors” Journal of Engineering & Computer Sciences, Vol 6, No. 1, pp. 33-49, 2013, ISSN:16584023.
  27. Yaseer A. Durrani “LUT-based power macromodelling technique for digital systems”, Punjab University Journal of Scientific Research, Vol. XXXX No.1, pp. 45-56, 2010, ISSN:0555-7674.
  28. N. Waheed, Yaseer A. Durrani, “Design of Efficient Photo-voltaic Cell” 32nd IEEEP National Engineering Student Competition, Feb, 2017, Karachi, Pakistan.
  29. S. Naseem, S. Riaz, M. Azam, S. S. Ali, Yaseer A. Durrani, “Power Macro Modeling for CMOS Inverter of 0.12 um Technology”, In Proceedings for International Conference on Advanced Computer Science and Electronics Information, pp. 509-513, July 2013, Beijing, China
  30. Yaseer A. Durrani, “Power Estimation Technique for Deep Submicrometer Conventional MOS Transistors”, In Proceedings for IEEE International Conference on Intelligent Engineering Systems, pp. 393-398, June 2011, Poprad, Slovakia
  31. Yaseer A. Durrani, “Efficient power macromodeling technique for Conventional MOS Transistors”, In Proceedings for International Conference on Electrical Engineering & Informatics , pp. 115-118, July 2011, Bundang, Indonesia (IEEE Sponsored)
  32. Yaseer A. Durrani, A. Abril, T. Riesgo, “Efficient power macromodeling technique for IP-based digital system”, In Proceedings for IEEE International Symposium on Circuits & Systems, pp. 1145-1148, May 2007, New Orleans, USA
  33. Yaseer A. Durrani, A. Abril, T. Riesgo, “High-level power estimation for digital system”, SPIE Proceedings of VLSI Circuits & Systems III, Vol. 6590, pp. 1-8, DOI:10.1117/12.721182, May 2007, (Invited Paper)
  34. Yaseer A. Durrani, “Architectural Power Macromodeling Technique for DSP Architectures”, In Proceedings for IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp. 255-260, April 2009, Cairo, Egypt
  35. Yaseer A. Durrani, “Accurate power estimation technique for DSP Architectures”, In Proceedings for IEEE International Symposium on Industrial Electronics, pp. 1123-1128, July 2009, Seoul, Korea
  36. Yaseer A. Durrani, “Efficient Power Optimization Technique for Array Multipliers”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 207-213, March 2010, Lahore, Pakistan
  37. S. Shahbaz, Yaseer A. Durrani, “Power Macromodelling for SRAM Cell Using 0.12um Technology”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 195-200, March 2010, Lahore, Pakistan
  38. B. Arif, Yaseer A. Durrani, “Power Macromodelling for DRAM Cell Using 0.12um Technology”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 215-217, March 2010, Lahore, Pakistan
  39. Yaseer A. Durrani, T. Riesgo, “Statistical power estimation for IP-based design”, In Proceedings for IEEE Conference on Industrial Electronics Society, pp. 4935-4939, Nov. 2006, Paris, France
  40. Yaseer A. Durrani, T. Riesgo, “LUT-Based Power Macromodeling Technique for DSP Architectures”, In Proceedings for IEEE International Conference on Electronics, Circuits and Systems, pp. 1416-1419, Dec. 2007, Morocco
  41. Yaseer A. Durrani, T. Riesgo, “Power macromodeling for IP modules”, In Proceedings for IEEE Intern. Conference on Electronics, Circuits & Systems, pp. 1172-1175, Dec. 2006, Nice, France
  42. Yaseer A. Durrani, A. Abril, T. Riesgo, “Architectural power estimation technique for IP-based system-on-chip”, In Proceedings for IEEE International Symposium on Industrial Electronics, pp. 2364-2368, June 2007, Vigo, Spain
  43. Yaseer A. Durrani, T. Riesgo, “Power estimation for IP-based modules”, In Proceeding for International Symposium on System-on-Chip, pp. 95-98, Nov. 2006, Tampere, Finland (IEEE Sponsored)
  44. Yaseer A. Durrani, T. Riesgo,“Statistical power estimation for register transfer level” , In Proceedings for International Conference on Mixed Design of Integrated Circuits and Systems, pp. 522-527, June 2006. Gdynia, Poland (IEEE Sponsored)
  45. Yaseer A. Durrani, T. Riesgo, “Power macromodeling for high level power estimation”, In Proceedings for International Workshop on Reconfigurable Communication-Centric System-on-Chip, pp. 232-236, July 2006. Montpellier, France
  46. Yaseer A. Durrani, T. Riesgo, “Power estimation for register transfer level by genetic algorithm”, In Proceedings for International Conference on Informatics in Control Automation and Robotics, pp. 527-530, Aug. 2006. Setubal, Portugal
  47. Yaseer A. Durrani, T. Riesgo, “High level statistical power estimation”, In Proceeding for International Workshop on Symbolic Method and Applications to Circuit Design”, Oct. 2006, Firenze, Italy
  48. Yaseer A. Durrani, T. Riesgo, A. Abril, “Power macromodeling technique for IP-based system”, In Proceeding for International Conference on Design of Circuits and Integrated Systems”, Nov. 2006, Barcelona, Spain
  • Chairman, Dept. of  Electronics Engineering, Main Campus, UET, Taxila (04-2018-to date)
  • Director of Post Graduate Studies & Industrial/External Linkage, Dept. of Electronics Engineering, UET, Taxila (03.2017-04-2018)
  • Chairman,Dept. of Electronics Enginering, Chakwal Campus, UET, Taxila  (05.2015-01.2017)
  • Chairman Electrical Engineering, University of the Punjab, Lahore (05.2009-10.2010)
  • UNIVERSITY OF ENGINEERING & TECHNOLOGY, TAXILA, PAKISTAN (08.2012-to date)
  • Associate Professor, Dept. of Electronics Engineering, Main Campus
  • Chairman Dept. of Electronics Enginering, Main Campus, (04-2018, to-date)
  • Chairman Dept. of Electronics Engineering, Chakwal Campus (05.2015-01.2017)
  • Research in Low Power Embedded System, VLSI/Nano Devices, Sensors & Bioelectronics
  • Teaching Courses: Electronics, M&I, VLSI, Embedded System Design
  • QASSIM UNIVERSITY, SAUDI ARABIA (11.2010-08.2012)
  • Assistant Professor
  • Research in Low Power Embedded System, VLSI/Nano Devices, Sensors & Bioelectronics
  • Teaching Courses: Electronics, M&I, Special Topics in Electronics, Embedded System Design
  • Member of the University Ranking System Committee
  • UNIVERSITY OF THE PUNJAB, PAKISTAN (05.2009-11.2010)
  • Assistant Professor/Chairman Dept. of Electrical Engineering
  • Administrative & Management Responsibilities
  • Research in Low Power Embedded System Design, VLSI/Nano Devices, Sensors & Bioelectronics
  • Teaching Graduate/Undergraduate Courses: Microelectronic Devices, VLSI Design, ASIC Design, Embedded Systems, Optical Fiber Communication, Computer Networking, Automation & Robotics
  • GIK INSTITUTE OF ENGINEERING SCIENCES & TECHNOLOGY, PAKISTAN (08.2008-05.2009
  • Assistant Professor
  • Research in Low Power Embedded Systems, VLSI, Nano Devices o Teaching Courses: Electronics, SoC Architecture, ASIC Design, Embedded Systems
  • RYERSON UNIVERSITY, CANADA (08.2007-04.2008)
  • Researcher
  • Research in Computer Architecture Design (Cache, SRAM, DRAM, Buffer, Decoder, Sense Amplifier ), Considering Propagation Delay, Latency, W/L, Voltage, Capacitances etc. o Transistor/Layout level Design using 0.09, 0.13 micron CMOS TechnologyUsing Cadence (Virtuoso, Schematic/Layout) Analog Design Environment Simulation, Synopsys (Power Compiler, Design Analyzer), Modelsim Tools
  • CELESTICA, CANADA (08.2007-04.2008)
  • Test Engineer
  • Functional Testing & Verification of several Alcatel Switches such as E1, T1, STM1-2M Cell Relay, Ethernet, Voice Band Service, Hub, I/O, Programmable Frame Relay, Circuit Simulation, Control Cards etc. o ICT, Test Probe In-Circuit & Functional Testing of Honeywell Aerospace PCBs, PCB Bonding o Test Procedures: SEEP, XILINX, ISP/LATTICS, APPLICATION DOWNLOAD, FIST etc. o Managements of Test Data Entry, Reports, Documentations & Organization
  • POLYTECHNIC UNIVERSITY OF MADRID, SPAIN (06.2002-06.2007)
  • Researcher
  • Low Power Digital CMOS Design at RTL (Using Circuit Optimization Techniques: Voltage, Frequency, Capacitance, Glitches etc.)
  • UNIVERSITY OF VICTORIA, CANADA (2005)
  • Researcher
  • Low Power SRAM Design for Intel’s XScale Microprocessor
  • INFINEON TECHNOLOGIES AG, GERMANY (2001)
  • Design Engineer
  • Full Custom Design of Layout Library Cells using 0.18 micron CMOS Technology of High Speed Applications for fabrication, Metal Oxide Semiconductors, Clock Tree Design o Hardware Verification, Integration, & Testing for RF Components
  • COSMO COMPUTER WORKS, PAKISTAN (1999-2000)
  • Computer Hardware Engineer
  • Responsible for System Support, Testing & Validation, Soldering, Hardware/Software Troubleshooting
  • PEC
  • IEEE
  • Advanced Engineering Mathematics
  • Solid State Electronics
  • System-on-Chip (SoC) Architecture
  • VLSI Design
  • Embedded System Design
  • Integrated Electronics
  • Microelectronic Devices & Technology
  • ASIC Design Methodologies
  • Instrumentation & Measurments
  • Chairman, Electronics Engineering Dept., Main Campus, UET, Taxila, (04-2018 to-date)
  • Director of Post Graduate Studies & Industrial/External Linkage, Dept. of Electronics Engineering, UET, Taxila (03.2017-to date)
  • Chairman Electronics Engineering, Dept. of Electronics Engineering, Chakwal Campus, UET, Taxila  (05.2015-01.2017)
  • Chairman Electrical Engineering, University of the Punjab, Lahore (05.2009-10.2010)
  • Director, Center of Excellence for ASIC Design & DSP Lab, UET, Taxila, Pakistan
  • Member of the University Ranking Committee, UET, Taxila, Pakistan
  • Member of the M.Sc. Admission Entry Test Committee, UET, Taxila, Pakistan
  • Member of the Electronics Department Semester Committee, UET, Taxila, Pakistan
  • Member of the University Ranking Committee, Qassim University, Saudi Arabia
  • Member of the Selection Committee, University of the Punjab, Lahore, Pakistan
  • Member of the Curriculum Revision Committee, University of the Punjab, Lahore, Pakistan
  • Member of the design of the PC-1 Committee, University of the Punjab, Lahore, Pakistan
  • Actively involved in Pakistan Engineering Council (PEC) Accreditation Team and visited several Universities in Pakistan
  • Univesity of Engineering & Technology, Taxila, Pakistan
  • University of the Punjab, Lahore, Pakistan
  • GIK Institute of Engineering Sciences & Technology, Topi, Pakistan
  • Qassim University, Qassim, Saudi Arabia
  • Polytechnic University of Madrid, Spain
  • Royal Institute of Technology, Sweden
  • Eastern Mediterrenean University, North Cyprus, Turkey
  • University of Victoria, Victoria, Canada
  • Ryerson University, Toronto, Canada
  • Two Years Scholarship Awarded by Royal Institute of Technology, Sweden
  • Five Years Scholarship Awarded by Polytechnic University of Madrid, Spain
  • Four months Research Scholarship Awarded by Polytechnic University of Madrid, Spain
  • Research Grant Awarded by Higher Education Commission (HEC), Pakistan (200,000 Rs.)(2008
  • Research Grant Awarded by University of the Punjab, Pakistan to establish Microelectronic Research Laboratory (40,00000 Rs.)(2009)
  • Research Grant Awarded by University of the Punjab, Pakistan (2,0000 Rs.)(2010)
  • Research Grant Awarded by University of the Punjab, Pakistan to establish Microelectronic Research Laboratory (60,00000 Rs.)(2010)
  • Research Grant Awarded by Higher Education Commission (HEC), Pakistan to establish Research Collaboration (400,000 Rs.)(2010)
  • Research Grant Award by Qassim University, Saudi Arabia (1,00000 SR) (2011)
  • Research Grant Award by UET, Taxila, Pakistan (8 Million Rs.) (2016)

 

  1. Yaseer A. Durrani,“Power Estimation Technique for Deep Submicrometer Conventional MOS Transistors”, In Proceedings for IEEE International Conference on Intelligent Engineering Systems, pp. 393-398, June 2011, Poprad, Slovakia
  2. S. Naseem, S. Riaz, M. Azam, S. S. Ali, Yaseer A. Durrani, “Power Macro Modeling for CMOS Inverter of 0.12 um Technology”, In Proceedings for International Conference on Advanced Computer Science and Electronics Information, pp. 509-513, July 2013, Beijing, China
  3. Yaseer A. Durrani, “Efficient power macromodeling technique for Conventional MOS Transistors”, In Proceedings for International Conference on Electrical Engineering & Informatics , pp. 115-118, July 2011, Bundang, Indonesia (IEEE Sponsored)
  4. Yaseer A. Durrani, A. Abril, T. Riesgo, “Efficient power macromodeling technique for IP-based digital system”, In Proceedings for IEEE International Symposium on Circuits & Systems, pp. 1145-1148, May 2007, New Orleans, USA
  5. Yaseer A. Durrani, A. Abril, T. Riesgo, “High-level power estimation for digital system”, SPIE Proceedings of VLSI Circuits & Systems III, Vol. 6590, pp. 1-8, DOI:10.1117/12.721182,  May 2007, (Invited Paper)
  6. Yaseer A. Durrani, “Architectural Power Macromodeling Technique for DSP Architectures”, In Proceedings for IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp. 255-260, April 2009, Cairo, Egypt
  7. Yaseer A. Durrani, “Accurate power estimation technique for DSP Architectures”, In Proceedings for IEEE International Symposium on Industrial Electronics, pp. 1123-1128, July 2009, Seoul, Korea
  8. Yaseer A. Durrani, “Efficient Power Optimization Technique for Array Multipliers”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 207-213,  March 2010, Lahore, Pakistan
  9. Shahbaz, Yaseer A. Durrani, “Power Macromodelling for SRAM Cell Using 0.12um Technology”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 195-200, March 2010, Lahore, Pakistan
  10. B. Arif, Yaseer A. Durrani, “Power Macromodelling for DRAM Cell Using 0.12um Technology”, In Proceedings for 3rd Symposium on Engineering Sciences, pp. 215-217, March 2010, Lahore, Pakistan
  11. Yaseer A. Durrani, T. Riesgo, “Statistical power estimation for IP-based design”, In Proceedings for IEEE Conference on Industrial Electronics Society, pp. 4935-4939, Nov. 2006, Paris, France
  12. Yaseer A. Durrani, T. Riesgo, “LUT-Based Power Macromodeling Technique for DSP Architectures”, In Proceedings for IEEE International Conference on Electronics, Circuits and Systems, pp. 1416-1419, Dec. 2007, Morocco
  13. Yaseer A. Durrani, T. Riesgo, “Power macromodeling for IP modules”, In Proceedings for IEEE Intern. Conference on Electronics, Circuits & Systems, pp. 1172-1175, Dec. 2006, Nice, France
  14. Yaseer A. Durrani, A. Abril, T. Riesgo, “Architectural power estimation technique for IP-based system-on-chip”, In Proceedings for IEEE International Symposium on Industrial Electronics, pp. 2364-2368, June 2007, Vigo, Spain
  15. Yaseer A. Durrani, T. Riesgo, “Power estimation for IP-based modules”, In Proceeding for International Symposium on System-on-Chip, pp. 95-98, Nov. 2006, Tampere, Finland (IEEE Sponsored)
  16. Yaseer A. Durrani, T. Riesgo,“Statistical power estimation for register transfer level” , In Proceedings for International Conference on Mixed Design of Integrated Circuits and Systems, pp. 522-527, June 2006. Gdynia, Poland (IEEE Sponsored)
  17. Yaseer A. Durrani, T. Riesgo, “Power macromodeling for high level power estimation”, In Proceedings for International Workshop on Reconfigurable Communication-Centric System-on-Chip, pp. 232-236, July 2006. Montpellier, France
  18. Yaseer A. Durrani, T. Riesgo, “Power estimation for register transfer level by genetic algorithm”, In Proceedings for International Conference on Informatics in Control Automation and Robotics, pp. 527-530, Aug. 2006. Setubal, Portugal
  19. Yaseer A. Durrani, T. Riesgo, “High level statistical power estimation”, In Proceeding for International Workshop on Symbolic Method and Applications to Circuit Design”, Oct. 2006, Firenze, Italy
  20. Yaseer A. Durrani, T. Riesgo, A. Abril, “Power macromodeling technique for IP-based system”, In Proceeding for International Conference on Design of Circuits and Integrated Systems”, Nov. 2006, Barcelona, Spain.

MSc. Thesis Supervised:

  • Thermal Power Modeling for Digital Systems, Zunaira Huma, 2015.
  • Power Analysis for Intellectual Property based Digital Systems, Amna Rauf, 2016.
  • Power Macro Modeling Approach for Network-on-Chip Design, Malik Tauqeer ul Hasan, 2017.
  • An Accurate Power Analysis Methodology for FPGA Devices, Awais Ali Shah, 2017.

Ph.D. Supervised:

  • Power Macro modeling for Digital System Design at High-Level, Faisal Siddique, (Since 2014-todate )
  • One year Diploma in Computer Science, University of Peshawar, (1991)
  • Two Years Intermediate Certificate in Commerce, Allama Iqbal Open University, Islamabad (1995)
  • Six Months Certificate in Electronic Developments, Peshawar Technical Board, Peshawar (1995)
  • PEC Outcome Based Education (OBE) Workshop (2016)
  • Xilinx Workshop on FPGAs with EDK (2005)

PhD. students:

  • Faisal Siddiq
  • Muhammad Ishaq
  • Muhammad Usman

MSc. Students:

  • Hadia Kiran
  • Dania Batool
  •